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MCP414X/416X/424X/426X
7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory
Features
* Single or Dual Resistor Network options * Potentiometer or Rheostat configuration options * Resistor Network Resolution - 7-bit: 128 Resistors (129 Steps) - 8-bit: 256 Resistors (257 Steps) * RAB Resistances options of: - 5 k - 10 k - 50 k - 100 k * Zero-Scale to Full-Scale Wiper operation * Low Wiper Resistance: 75 (typical) * Low Tempco: - Absolute (Rheostat): 50 ppm typical (0C to 70C) - Ratiometric (Potentiometer): 15 ppm typical * Non-volatile Memory - Automatic Recall of Saved Wiper Setting - WiperLockTM Technology * SPI serial interface (10 MHz, modes 0,0 & 1,1) - High-Speed Read/Writes to wiper registers - Read/Write to Data EEPROM registers - Serially enabled EEPROM write protect - SDI/SDO multiplexing (MCP41X1 only) * Resistor Network Terminal Disconnect Feature via: - Shutdown pin (SHDN) - Terminal Control (TCON) Register * Write Protect Feature: - Hardware Write Protect (WP) Control pin - Software Write Protect (WP) Configuration bit * Brown-out reset protection (1.5V typical) * Serial Interface Inactive current (2.5 uA typical) * High-Voltage Tolerant Digital Inputs: Up to 12.5V * Supports Split Rail Applications * Internal weak pull-up on all digital inputs * Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation * Wide Bandwidth (-3dB) Operation: - 2 MHz (typical) for 5.0 k device * Extended temperature range (-40C to +125C)
Description
The MCP41XX and MCP42XX devices offer a wide range of product offerings using an SPI interface. WiperLock Technology allows application-specific calibration settings to be secured in the EEPROM.
Package Types (top view)
MCP41X1 Single Potentiometer
CS SCK SDI/SDO VSS
1 2 3 4
8 7 6 5
VDD P0B P0W P0A
MCP41X2 Single Rheostat CS 1 8 VDD SCK 2 7 SDO SDI 3 6 P0B 5 P0W VSS 4 PDIP, SOIC, MSOP
CS 1 SCK 2 SDI 3 VSS 4 EP 9 8 VDD 7 SDO 6 P0B 5 P0W
PDIP, SOIC, MSOP
CS 1 SCK 2 SDI/SDO 3 VSS 4 EP 9 8 VDD 7 P0B 6 P0W 5 P0A
3x3 DFN*
3x3 DFN*
CS SCK SDI VSS P1B P1W P1A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD SDO SCK SHDN SDI WP P0B VSS P0W V SS P0A
16 15 14 13 1 2 3 4 5 P1B 6 P1W 7 P1A 8 P0A 10 VDD EP 11 9 SDO 8 P0B 7 P0W 6 P1W EP 17 12 WP 11 NC 10 P0B 9 P0W
PDIP, SOIC, TSSOP
4x4 QFN* MCP42X2 Dual Rheostat
CS SCK SDI VSS P1B
1 2 3 4 5
10 9 8 7 6
CS 1 VDD SDO SCK 2 P0B P0W SDI 3 P1W VSS 4 P1B 5
MSOP, DFN
3x3 DFN*
* Includes Exposed Thermal Pad (EP); see Table 3-1.
(c) 2008 Microchip Technology Inc.
DS22059B-page 1
SHDN
MCP42X1 Dual Potentiometers
SDO VDD CS
MCP414X/416X/424X/426X
Device Block Diagram
VDD VSS CS SCK SDI SDO WP SHDN For Dual Potentiometer Devices Only Power-up/ Brown-out Control SPI Serial Interface Module & Control Logic (WiperLockTM Technology) P0A P0W
Resistor Network 0 (Pot 0) Wiper 0 & TCON Register
P0B P1A P1W
Resistor Network 1 (Pot 1) Wiper 1 & TCON Register For Dual Resistor Network Devices Only
Memory (16x9) Wiper0 (V & NV) Wiper1 (V & NV) TCON STATUS Data EEPROM (10 x 9-bits)
P1B
Device Features
WiperLock Technology POR Wiper Setting # of Steps # of POTs Control Interface Memory Type Resistance (typical) RAB Options (k) Wiper - RW () 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 Wiper Configuration VDD Operating Range (2)
Device
MCP4131 (3) MCP4132 (3) MCP4141 MCP4142 MCP4151 (3) MCP4152 (3) MCP4161 MCP4162 MCP4231 (3) MCP4232 MCP4241 MCP4242 MCP4251 (3) MCP4252 (3) MCP4261 MCP4262 Note 1: 2: 3:
(3)
1 Potentiometer (1) SPI 1 1 1 1 2 2 2 2 Rheostat Rheostat Rheostat Rheostat Rheostat Rheostat Rheostat Rheostat SPI SPI SPI SPI SPI SPI SPI SPI 1 Potentiometer (1) SPI 1 Potentiometer (1) SPI 1 Potentiometer (1) SPI 2 Potentiometer (1) SPI 2 Potentiometer (1) SPI 2 Potentiometer (1) SPI 2 Potentiometer (1) SPI
RAM RAM EE EE RAM RAM EE EE RAM RAM EE EE RAM RAM EE EE
No No Yes Yes No No Yes Yes No No Yes Yes No No Yes Yes
Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 Mid-Scale 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0 NV Wiper 5.0, 10.0, 50.0, 100.0
129 1.8V to 5.5V 129 1.8V to 5.5V 129 2.7V to 5.5V 129 2.7V to 5.5V 257 1.8V to 5.5V 257 1.8V to 5.5V 257 2.7V to 5.5V 257 2.7V to 5.5V 129 1.8V to 5.5V 129 1.8V to 5.5V 129 2.7V to 5.5V 129 2.7V to 5.5V 257 1.8V to 5.5V 257 1.8V to 5.5V 257 2.7V to 5.5V 257 2.7V to 5.5V
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. Please check Microchip web site for device release and availability
DS22059B-page 2
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
1.0 ELECTRICAL CHARACTERISTICS
Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Voltage on VDD with respect to VSS ............... -0.6V to +7.0V Voltage on CS, SCK, SDI, SDI/SDO, WP, and SHDN with respect to VSS ...................................... -0.6V to 12.5V Voltage on all other pins (PxA, PxW, PxB, and SDO) with respect to VSS ............................ -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ......................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ..................................................20 mA Maximum output current sunk by any Output pin ......................................................................................25 mA Maximum output current sourced by any Output pin ......................................................................................25 mA Maximum current out of VSS pin .................................100 mA Maximum current into VDD pin ....................................100 mA Maximum current into PXA, PXW & PXB pins ............2.5 mA Storage temperature ....................................-65C to +150C Ambient temperature with power applied .....................................................................-40C to +125C Total power dissipation (Note 1) ................................400 mW Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins .................................. 4 kV (HBM), .......................................................................... 300V (MM) Maximum Junction Temperature (TJ) ......................... +150C
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOI x IOL)
(c) 2008 Microchip Technology Inc.
DS22059B-page 3
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VDD VHV Min 2.7 1.8 CS, SDI, SDO, SCK, WP, SHDN pin Voltage Range VDD Start Voltage to ensure Wiper Reset VDD Rise Rate to ensure Power-on Reset Delay after device exits the reset state (VDD > VBOR) Supply Current (Note 10) VSS VSS VBOR -- Typ -- -- -- -- -- Max 5.5 2.7 12.5V VDD + 8.0V 1.65 Units V V V V V Serial Interface only. VDD 4.5V VDD < 4.5V The CS pin will be at one of three input levels (VIL, VIH or VIHH). (Note 6) Conditions
Parameters Supply Voltage
RAM retention voltage (VRAM) < VBOR
VDDRR
(Note 9)
V/ms
TBORD
--
10
20
s
IDD
--
--
450
A
Serial Interface Active, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 (address 0h) EE Write Current, VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to non-volatile Wiper 0 (address 2h) Serial Interface Inactive, CS = VIH, VDD = 5.5V Serial Interface Active, VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement non-volatile Wiper 0 (address 2h)
--
--
1
mA
-- --
2.5 0.55
5 1
A mA
Note 1: 2: 3: 4: 5: 6: 7:
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
DS22059B-page 4
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym RAB Min 4.0 8.0 40.0 80.0 Resolution Step Resistance N RS -- -- Nominal Resistance Match |RAB0 - RAB1| / RAB |RBW0 - RBW1| / RBW Wiper Resistance (Note 3, Note 4) Nominal Resistance Tempco Ratiometeric Tempco Resistor Terminal Input Voltage Range (Terminals A, B and W) Maximum current through A, W or B Leakage current into A, W or B Note 1: 2: 3: 4: 5: 6: 7: RW RAB/T -- -- -- -- -- -- -- VWB/T VA,VW,VB -- Vss Typ 5 10 50 100 257 129 RAB / (256) RAB / (128) 0.2 0.25 75 75 50 100 150 15 -- -- -- 1.25 1.5 160 300 -- -- -- -- VDD Max 6.0 12.0 60.0 120.0 Units k k k k Taps Taps % % Conditions -502 devices (Note 1) -103 devices (Note 1) -503 devices (Note 1) -104 devices (Note 1) 8-bit 7-bit 8-bit 7-bit No Missing Codes No Missing Codes Note 6 Note 6
Parameters Resistance ( 20%)
MCP42X1 devices only MCP42X2 devices only, Code = Full-Scale VDD = 5.5 V, IW = 2.0 mA, code = 00h VDD = 2.7 V, IW = 2.0 mA, code = 00h
ppm/C TA = -20C to +70C ppm/C TA = -40C to +85C ppm/C TA = -40C to +125C ppm/C Code = Midscale (80h or 40h) V Note 5, Note 6
IW
--
--
2.5
mA
Note 6, Worst case current through wiper when wiper is either Full-Scale or Zero Scale. MCP4XX1 PxA = PxW = PxB = VSS MCP4XX2 PxB = PxW = VSS
IWL
-- --
100 100
-- --
nA nA
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
(c) 2008 Microchip Technology Inc.
DS22059B-page 5
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VWFSE Min -6.0 -4.0 -3.5 -2.0 -0.8 -0.5 -0.5 -0.5 Zero-Scale Error (MCP4XX1 only) (8-bit code = 00h, 7-bit code = 00h) VWZSE -- -- -- -- -- -- -- -- Potentiometer Integral Non-linearity Potentiometer Differential Non-linearity Bandwidth -3 dB (See Figure 2-58, load = 30 pF) INL -1 -0.5 DNL -0.5 -0.25 BW -- -- -- -- -- -- -- -- Note 1: 2: 3: 4: 5: 6: 7: Typ -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 0.5 0.25 0.25 0.125 2 2 1 1 200 200 100 100 Max -- -- -- -- -- -- -- -- +6.0 +3.0 +3.5 +2.0 +0.8 +0.5 +0.5 +0.5 +1 +0.5 +0.5 +0.25 -- -- -- -- -- -- -- -- Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb MHz MHz MHz MHz kHz kHz kHz kHz 50 k 10 k 8-bit 7-bit 8-bit 7-bit 5 k 50 k 10 k 5 k 50 k 10 k 5 k 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 100 k 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit 100 k 8-bit 7-bit Conditions 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V 3.0V VDD 5.5V
Parameters Full-Scale Error (MCP4XX1 only) (8-bit code = 100h, 7-bit code = 80h)
3.0V VDD 5.5V MCP4XX1 devices only (Note 2) 3.0V VDD 5.5V MCP4XX1 devices only (Note 2) 8-bit 7-bit 8-bit 7-bit 8-bit 7-bit Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h Code = 80h Code = 40h
100 k 8-bit 7-bit
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
(c) 2008 Microchip Technology Inc.
DS22059B-page 6
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-INL Min -1.5 -8.25 -1.125 -6.0 -1.5 -5.5 -1.125 -4.0 -1.5 -2.0 -1.125 -1.5 -1.0 -1.5 -0.8 -1.125 Note 1: 2: 3: 4: 5: 6: 7: Typ 0.5 +4.5 0.5 +4.5 0.5 +2.5 0.5 +2.5 0.5 +1 0.5 +1 0.5 +0.25 0.5 +0.25 Max +1.5 +8.25 +1.125 +6.0 +1.5 +5.5 +1.125 +4.0 +1.5 +2.0 +1.125 +1.5 +1.0 +1.5 +0.8 +1.125 Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb 7-bit 100 k 8-bit 7-bit 50 k 8-bit 7-bit 10 k 8-bit 7-bit 5 k 8-bit Conditions 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7)
Parameters Rheostat Integral Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
(c) 2008 Microchip Technology Inc.
DS22059B-page 7
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym R-DNL Min -0.5 -1.0 -0.375 -0.75 -0.5 -1.0 -0.375 -0.75 -0.5 -0.5 -0.375 -0.375 -0.5 -0.5 -0.375 -0.375 Capacitance (PA) Capacitance (Pw) Capacitance (PB) Note 1: 2: 3: 4: 5: 6: 7: CAW CW CBW -- -- -- Typ 0.25 +0.5 0.25 +0.5 0.25 +0.25 0.25 +0.5 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 75 120 75 Max +0.5 +1.0 +0.375 +0.75 +0.5 +1.0 +0.375 +0.75 +0.5 +0.5 +0.375 +0.375 +0.5 +0.5 +0.375 +0.375 -- -- -- Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb pF pF pF 7-bit 100 k 8-bit 7-bit 50 k 8-bit 7-bit 10 k 8-bit 7-bit 5 k 8-bit Conditions 5.5V, IW = 900 A 3.0V (Note 7) 5.5V, IW = 900 A 3.0V (Note 7) 5.5V, IW = 450 A 3.0V (Note 7) 5.5V, IW = 450 A 3.0V (Note 7) 5.5V, IW = 90 A 3.0V (Note 7) 5.5V, IW = 90 A 3.0V (Note 7) 5.5V, IW = 45 A 3.0V (Note 7) 5.5V, IW = 45 A 3.0V (Note 7) f =1 MHz, Code = Full-Scale f =1 MHz, Code = Full-Scale f =1 MHz, Code = Full-Scale
Parameters Rheostat Differential Non-linearity MCP41X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4)
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
DS22059B-page 8
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym VIH Min 0.45 VDD Typ -- Max -- Units V Conditions 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 1.8V VDD 2.7V
Parameters Schmitt Trigger High Input Threshold Schmitt Trigger Low Input Threshold Hysteresis of Schmitt Trigger Inputs High Voltage Input Entry Voltage High Voltage Input Exit Voltage High Voltage Limit Output Low Voltage (SDO) Output High Voltage (SDO) Weak Pull-up / Pull-down Current CS Pull-up / Pull-down Resistance Input Leakage Current Pin Capacitance Note 1: 2: 3: 4: 5: 6: 7:
Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, SHDN)
0.5 VDD VIL --
-- --
-- 0.2VDD
V V
VHYS
--
0.1VDD
--
V
VIHH VIHH VMAX VOL VOH IPU
8.5 -- -- VSS VSS 0.7VDD 0.7VDD -- --
-- -- -- -- -- -- -- -- 170 16
12.5 (6) VDD + 0.8V (6) 12.5 (6) 0.3VDD 0.3VDD VDD VDD 1.75 -- --
V V V V V V V mA A k
Threshold for WiperLockTM Technology
Pin can tolerate VMAX or less. IOL = 5 mA, VDD = 5.5V IOL = 1 mA, VDD = 1.8V IOH = -2.5 mA, VDD = 5.5V IOL = -1 mA, VDD = 1.8V Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V CS pin, VDD = 5.5V, VCS = 3V VDD = 5.5V, VCS = 3V
RCS
--
IIL CIN, COUT
-1 --
-- 10
1 --
A pF
VIN = VDD and VIN = VSS fC = 20 MHz
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
(c) 2008 Microchip Technology Inc.
DS22059B-page 9
MCP414X/416X/424X/426X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym N Min 0h 0h EEPROM Endurance EEPROM Range Initial Factory Setting EEPROM Programming Write Cycle Time Power Requirements Power Supply Sensitivity (MCP41X2 and MCP42X2 only) Note 1: 2: 3: 4: 5: 6: 7: PSS -- -- 0.0015 0.0015 0.0035 0.0035 %/% %/% 8-bit 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h Endurance N N tWC -- -- 0h 1M -- 80h 40h 5 10 -- 1FFh Cycles hex hex hex ms 8-bit 7-bit WiperLock Technology = Off WiperLock Technology = Off Typ -- -- Max 1FFh 1FFh Units hex hex 8-bit device 7-bit device Conditions
Parameters RAM (Wiper) Value Value Range
Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network
DS22059B-page 10
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
1.1 SPI Mode Timing Waveforms and Requirements
VIH CS 70 SCK 72
VIHH VIL
VIH
84
83 71 80 SDO MSb 75, 76 SDI 73 MSb IN 74 BIT6 - - - -1 LSb IN 79 BIT6 - - - - - -1 78 LSb 77
FIGURE 1-1: TABLE 1-1:
#
SPI Timing Waveform (Mode = 11). SPI REQUIREMENTS (MODE = 11)
Characteristic Symbol FSCK TcsA2scH TscH TscL TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV TscH2csI TcsA2csI Min -- -- 60 45 500 45 500 10 20 -- -- 100 1 50 Max Units 10 1 -- -- -- -- -- -- -- 50 70 170 -- -- MHz MHz ns ns ns ns ns ns ns ns ns ns ns ms ns Conditions VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
SCK Input Frequency 70 71 72 73 74 77 80 83 84 CS Active (VIL or VIHH) to SCK input SCK input high time SCK input low time Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output hi-impedance SDO data output valid after SCK edge CS Inactive (VIH) after SCK edge
Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) Note 1: This specification by design.
(c) 2008 Microchip Technology Inc.
DS22059B-page 11
MCP414X/416X/424X/426X
VIH CS 70 83 71 SDO MSb 75, 76 MSb IN 74 BIT6 - - - -1 LSb IN 72 BIT6 - - - - - -1 80 LSb 77 VIHH 82 VIL VIH 84
SCK
73 SDI
FIGURE 1-2: TABLE 1-2:
#
SPI Timing Waveform (Mode = 00). SPI REQUIREMENTS (MODE = 00)
Characteristic Symbol FSCK TcsA2scH TscH TscL TDIV2scH TscH2DIL TcsH2DOZ TscL2DOV TssL2doV TscH2csI TcsA2csI Min -- -- 60 45 500 45 500 10 20 -- -- -- 100 1 50 Max Units 10 1 -- -- -- -- -- -- -- 50 70 170 70 -- -- MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ms ns Conditions VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
SCK Input Frequency 70 71 72 73 74 77 80 82 83 84 CS Active (VIL or VIHH) to SCK input SCK input high time SCK input low time Setup time of SDI input to SCK edge Hold time of SDI input from SCK edge CS Inactive (VIH) to SDO output hi-impedance SDO data output valid after SCK edge SDO data output valid after CS Active (VIL or VIHH) CS Inactive (VIH) after SCK edge
Note 1 VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
VDD = 2.7V to 5.5V VDD = 1.8V to 2.7V
Hold time of CS Inactive (VIH) to CS Active (VIL or VIHH) Note 1: This specification by design.
DS22059B-page 12
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
TABLE 1-3: SPI REQUIREMENTS FOR SDI/SDO MULTIPLEXED (READ OPERATION ONLY) (2)
Characteristic Symbol Min Max Units Conditions
-- 250 kHz VDD= 2.7V to 5.5V SCK Input Frequency FSCK TcsA2scH 60 -- ns CS Active (VIL or VIHH) to SCK input SCK input high time TscH 1.8 -- us SCK input low time TscL 1.8 -- ns 40 -- ns Setup time of SDI input to SCK edge TDIV2scH 40 -- ns Hold time of SDI input from SCK edge TscH2DIL CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ -- 50 ns Note 1 -- 1.6 us SDO data output valid after SCK edge TscL2DOV TssL2doV -- 50 ns SDO data output valid after CS Active (VIL or VIHH) TscH2csI 100 -- ns CS Inactive (VIH) after SCK edge TcsA2csI 50 -- ns Hold time of CS Inactive (VIH) to CS Active (VII or VIHH) Note 1: This specification by design 2: This table is for the devices where the SPI's SDI and SDO pins are multiplexed (SDI/SDO) and a Read command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write commands. This data rate can be increased by having external pull-up resistors to increase the rising edges of each bit.
(c) 2008 Microchip Technology Inc.
DS22059B-page 13
MCP414X/416X/424X/426X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-DFN (3x3) Thermal Resistance, 10L-DFN (3x3) Thermal Resistance, 10L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-QFN JA JA JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- -- -- 211 89.3 149.5 60 57 202 70 95.3 100 43 -- -- -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Sym Min Typ Max Units Conditions
DS22059B-page 14
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
650 600 550 500 450 400 350 300 250 200 150 100 50 0 0.00
Operating Current (I DD) (A)
RCS (kOhms)
100 50
RCS
0 2.00 4.00 6.00 8.00 fSCK (MHz) 10.00 12.00 2 3 4 5 6 7 VCS (V) 8 9 10
FIGURE 2-1: Device Current (IDD) vs. SPI Frequency (fSCK) and Ambient Temperature (VDD = 2.7V and 5.5V).
3.0 Standby Current (Istby) (A)
FIGURE 2-4: CS Pull-up/Pull-down Resistance (RCS) and Current (ICS) vs. CS Input Voltage (VCS) (VDD = 5.5V).
12
CS V PP Threshold (V)
2.5 2.0 1.5 1.0 0.5 0.0 -40 25 85 125 Ambient Temperature (C)
2.7V 5.5V
10
5.5V Entry
8 6 4
2.7V Exit 5.5V Exit
2.7V Entry
2 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) 100 120
FIGURE 2-2: Device Current (ISHDN) and VDD. (CS = VDD) vs. Ambient Temperature.
900.0 EE Write Current (Iwrite) (A) 800.0 700.0 600.0 500.0 400.0 300.0 -40 25 85 125 Ambient Temperature (C)
5.5V
FIGURE 2-5: CS High Input Entry/Exit Threshold vs. Ambient Temperature and VDD.
FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature and VDD.
(c) 2008 Microchip Technology Inc.
DS22059B-page 15
ICS (A)
2.7V -40C 2.7V 25C 2.7V 85C 2.7V 125C 5.5V -40C 5.5V 25C 5.5V 85C 5.5V 125C
250 200 150
ICS
1000 800 600 400 200 0 -200 -400 -600 -800 -1000
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (RW) (ohms) 100 80 0 60 -0.1 40
125C 85C -40C 25C
Wiper Resistance (RW) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
120 100 80 60 40
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1.25 0.75 0.25 -0.25 Error (LSb) Error (LSb)
256
DNL
INL
INL
RW
-0.2
125C
85C 25C
-40C
DNL RW
-0.75
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-1.25 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-6: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 0 140 100 60
-40C 25C 85C RW 125C
FIGURE 2-9: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (RW) (ohms) 260 220 180 140
RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
6 4 2 0
INL DNL
INL
-0.1 -0.2
100 60
125C 85C -40C 25C
DNL
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-2 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-7: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
5300
AB)
FIGURE 2-10: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
6000 5000
Nominal Resistance (R (Ohms)
5250 5200 5150 5100
5.5V
RWB (Ohms)
2.7V
4000 3000 2000 1000 0
-40C 25C 85C 125C
5050 -40 0 40 80 Ambient Temperature (C) 120
0
32
64 96 128 160 192 Wiper Setting (decimal)
224
FIGURE 2-8: 5 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-11: 5 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22059B-page 16
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-12: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-15: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-13: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-16: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-14: 5 k - Power-Up Wiper Response Time (20 ms/Div).
(c) 2008 Microchip Technology Inc.
DS22059B-page 17
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 0 60 -0.1 40 20 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal)
25C -40C 125C 85C RW
0.2 Error (LSb) 0.1
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
1
0.5 Error (LSb)
256
INL
DNL
INL
0 60 40
125C -40C RW DNL
-0.5
-0.2 -0.3
85C 25C
20 0 32
-1 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-17: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 0 140 100 60 20 0
25C 125C 85C -40C RW
FIGURE 2-20: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 1 140 100 60
125C 85C 25C -40C DNL RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
4 3 Error (LSb) 2
INL
DNL
INL
-0.1 -0.2
0 -1 -2 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal)
32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20
FIGURE 2-18: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
10250
AB)
FIGURE 2-21: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
12000 10000
Nominal Resistance (R (Ohms)
10200 10150
2.7V
RWB (Ohms)
8000 6000 4000 2000 0
-40C 25C 85C 125C
10100
5.5V
10050 10000 -40 0 40 80 Ambient Temperature (C) 120
0
32
64 96 128 160 192 Wiper Setting (decimal)
224
FIGURE 2-19: 10 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-22: 10 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22059B-page 18
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-23: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-25: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-24: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-26: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
(c) 2008 Microchip Technology Inc.
DS22059B-page 19
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 0 60 -0.1 40
125C 25C 85C -40C RW
0.2 Error (LSb) 0.1
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3
120 100 80
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) Error (LSb) 0.1 0
DNL
INL
INL DNL
60 -0.1 40
125C 85C 25C -40C RW
-0.2
-0.2
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-27: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 0 140 100 60 20 0
125C 85C 25C -40C RW
FIGURE 2-30: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 140 100 60
125C -40C 85C 25C RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) 0.1
1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75
INL DNL
DNL
INL
-0.1 -0.2
32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32 64
-1 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-28: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
50800
AB)
FIGURE 2-31: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
60000 50000
50600
Nominal Resistance (R (Ohms)
50200 50000
5.5V
2.7V
RWB (Ohms)
50400
40000 30000 20000 10000 0
-40C 25C 85C 125C
49800 49600 49400 -40 0 40 80 Ambient Temperature (C) 120
0
32
64 96 128 160 192 Wiper Setting (decimal)
224
256
FIGURE 2-29: 50 k - Nominal Resistance () vs. Ambient Temperature and VDD.
FIGURE 2-32: 50 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22059B-page 20
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-33: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-35: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-34: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-36: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div).
(c) 2008 Microchip Technology Inc.
DS22059B-page 21
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
120 Wiper Resistance (R W) (ohms) 100 80 60 40 20 0 32 -0.1
25C -40C 125C 85C RW
Wiper Resistance (R W) (ohms)
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2
120 100 80 60
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.3 0.2 Error (LSb) Error (LSb) 0.1 0 -0.1
Error (LSb)
INL DNL
0.1
INL DNL
0
40
125C 85C 25C
-40C
RW
-0.2
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
20 0 32
-0.3 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-37: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (R W) (ohms) 260 220 180 140 100 60 20 0
125C 85C 25C -40C RW
FIGURE 2-40: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V).
300 Wiper Resistance (Rw) (ohms) 260 220 180 0 140 100 60 20 0
125C 85C 25C -40C RW
-40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL
-40C Rw -40C INL -40C DNL
25C Rw 25C INL 25C DNL
85C Rw 85C INL 85C DNL
125C Rw 125C INL 125C DNL
0.2 0.15 0.1 0.05 0 Error (LSb)
0.6 0.4 0.2
INL DNL
INL DNL
-0.05 -0.1 -0.15
-0.2 -0.4
32
-0.2 64 96 128 160 192 224 256 Wiper Setting (decimal)
32
-0.6 64 96 128 160 192 224 256 Wiper Setting (decimal)
FIGURE 2-38: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
101500
AB)
FIGURE 2-41: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V).
120000 100000
Nominal Resistance (R (Ohms)
101000 Rwb (Ohms) 100500 100000 99500 99000 -40 0 40 80 Ambient Temperature (C) 120
5.5V
80000 60000 40000 20000 0 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256
-40C 25C 85C 125C
2.7V
FIGURE 2-39: 100 k - Nominal Resistance () vs. Ambient Temperature and VDD .
FIGURE 2-42: 100 k - RWB () vs. Wiper Setting and Ambient Temperature.
DS22059B-page 22
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
FIGURE 2-43: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div).
FIGURE 2-45: 100 k - Power-Up Wiper Response Time (1 s/Div).
FIGURE 2-44: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div).
FIGURE 2-46: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div).
(c) 2008 Microchip Technology Inc.
DS22059B-page 23
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
0.12 0.1
5.5V
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 -40
0.08
%
5.5V
%
0.06 0.04 0.02 0
3.0V
3.0V
0
40 80 Temperature (C)
120
-40
0
40 80 Temperature (C)
120
FIGURE 2-47: Resistor Network 0 to Resistor Network 1 RAB (5 k) Mismatch vs. VDD and Temperature.
FIGURE 2-49: Resistor Network 0 to Resistor Network 1 RAB (50 k) Mismatch vs. VDD and Temperature.
0.04 0.03 0.02 0.01 % 0 -0.01 -0.02 -0.03 -0.04 -40 0 40 80 Temperature (C) 120
3.0V 5.5V
0.05 0.04 0.03 0.02
%
5.5V
0.01 0 -0.01 -0.02 -0.03 -40 10 60 Temperature (C) 110
3.0V
FIGURE 2-48: Resistor Network 0 to Resistor Network 1 RAB (10 k) Mismatch vs. VDD and Temperature.
FIGURE 2-50: Resistor Network 0 to Resistor Network 1 RAB (100 k) Mismatch vs. VDD and Temperature.
DS22059B-page 24
(c) 2008 Microchip Technology Inc.
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
2.4 2.2 2 VIH (V) 1.8 1.6 1.4 1.2 1 -40 0 40 Temperature (C) 80 120
2.7V 5.5V
0 -5 -10 IOH (mA) -15 -20 -25 -30 -35 -40 -45 -40 0 40 Temperature (C) 80 120
5.5V 2.7V
FIGURE 2-51: VIH (SDI, SCK, CS, WP, and SHDN) vs. VDD and Temperature.
1.4 1.3 1.2 VIL (V) 1.1 1 0.9 0.8 0.7 0.6 -40 0 40 Temperature (C) 80 120
2.7V 5.5V
FIGURE 2-53: Temperature.
50 45 40 35 30 25 20 15 10 5 0 -40 0
IOH (SDO) vs. VDD and
5.5V
IOL (mA)
2.7V
40 Temperature (C)
80
120
FIGURE 2-52: VIL (SDI, SCK, CS, WP, and SHDN) vs. VDD and Temperature.
FIGURE 2-54: Temperature.
IOL (SDO) vs. VDD and
(c) 2008 Microchip Technology Inc.
DS22059B-page 25
MCP414X/416X/424X/426X
Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V.
4.2 4.0 tWC (ms) 3.8 3.6 3.4 3.2 3.0 -40 0 40 Temperature (C) 80 120
2.1
Test Circuits
+5V VIN Offset GND A B W + VOUT
2.5V DC
FIGURE 2-55: Nominal EEPROM Write Cycle Time vs. VDD and Temperature.
1.2 1 0.8 VDD (V) 0.6 0.4 0.2 0 -40 0 40 Temperature (C) 80 120
2.7V 5.5V
FIGURE 2-58: Test.
-3 db Gain vs. Frequency
FIGURE 2-56: and Temperature.
15.0 14.5
POR/BOR Trip point vs. VDD
5.5V
fsck (MHz)
14.0 13.5 13.0 12.5 12.0 -40 0 40 Temperature (C) 80 120
2.7V
FIGURE 2-57: SCK Input Frequency vs. Voltage and Temperature.
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3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP414X/416X/424X/426X
Pin Weak Pull-up/ down (Note 2) "smart" "smart" "smart" "smart" -- No No No No No No "smart" "smart" No -- -- --
Single Rheo Pot (1) Rheo 8L 1 2 3 -- 4 -- -- -- -- 5 6 -- -- 7 8 -- 9 Legend: 8L 1 2 -- 3 4 -- -- -- 5 6 7 -- -- -- 8 -- 9 10L 1 2 3 -- 4 5 6 -- -- 7 8 -- -- 9 10 -- 11
Dual Pot 14L 1 2 3 -- 4 5 6 7 8 9 10 11 12 13 14 -- -- 16L 16 1 2 -- 3, 4 5 6 7 8 9 10 12 13 14 15 11 17 CS SCK SDI SDI/SDO VSS P1B P1W P1A P0A P0W P0B WP SHDN SDO VDD NC EP I I I I/O -- A A A A A A I I O -- -- -- HV w/ST HV w/ST HV w/ST HV w/ST P Analog Analog Analog Analog Analog Analog I HV w/ST O P -- -- Symbol I/O Buffer Type
Standard Function
SPI Chip Select Input SPI Clock Input SPI Serial Data Input SPI Serial Data Input/Output (Note 1, Note 3) Ground Potentiometer 1 Terminal B Potentiometer 1 Wiper Terminal Potentiometer 1 Terminal A Potentiometer 0 Terminal A Potentiometer 0 Wiper Terminal Potentiometer 0 Terminal B Hardware Protect EEPROM Write
Hardware Shutdown SPI Serial Data Out Positive Power Supply Input No Connection Exposed Pad. (Note 4)
HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin (SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin. The pin's "smart" pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. The SDO is an open drain output, which uses the internal "smart" pull-up. The SDI input data rate can be at the maximum SPI frequency. the SDO output data rate will be limited by the "speed" of the pull-up, customers can increase the rate with external pull-up resistors. The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin.
Note 1:
2: 3:
4:
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3.1 Chip Select (CS) 3.7 Potentiometer Terminal A
The CS pin is the serial interface's chip select input. Forcing the CS pin to VIL enables the serial commands. Forcing the CS pin to VIHH enables the high-voltage serial commands. The terminal A pin is available on the MCP4XX1 devices, and is connected to the internal potentiometer's terminal A. The potentiometer's terminal A is the fixed connection to the Full Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4XX2 devices, and the internally terminal A signal is floating. MCP42X1 devices have two terminal A pins, one for each resistor network.
3.2
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin. This pin is connected to the Host Controllers SDO pin.
3.3
Serial Data In / Serial Data Out (SDI/SDO)
On the MCP41X1 devices, pin-out limitations do not allow for individual SDI and SDO pins. On these devices, the SDI and SDO pins are multiplexed. The MCP41X1 serial interface knows when the pin needs to change from being an input (SDI) to being an output (SDO). The Host Controller's SDO pin must be properly protected from a drive conflict.
3.8
Write Protect (WP)
The WP pin is used to force the non-volatile memory to be write protected.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.9
Shutdown (SHDN)
3.5
Potentiometer Terminal B
The SHDN pin is used to force the resistor network terminals into the hardware shutdown state.
The terminal B pin is connected to the internal potentiometer's terminal B. The potentiometer's terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP42XX devices have two terminal B pins, one for each resistor network.
3.10
Serial Data Out (SDO)
The SDO pin is the serial interfaces Serial Data Out pin. This pin is connected to the Host Controllers SDI pin. This pin allows the Host Controller to read the digital potentiometers registers, or monitor the state of the command error bit.
3.11
Positive Power Supply Input (VDD)
The VDD pin is the device's positive power supply input. The input power supply is relative to VSS. While the device VDD < Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications.
3.6
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. MCP42XX devices have two terminal W pins, one for each resistor network.
3.12
No Connection (NC)
Those pins should be either connected to VDD or VSS.
3.13
Exposed Pad (EP)
This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink.
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4.0 FUNCTIONAL OVERVIEW
4.1.2 BROWN-OUT RESET
This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: * * * * POR/BOR Operation Memory Map Resistor Network Serial Interface (SPI) When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the following happens: * Serial Interface is disabled * EEPROM Writes are disabled If the VDD voltage decreases below the VRAM voltage the following happens: * Volatile wiper registers may become corrupted * TCON register may become corrupted As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 "Power-on Reset". Serial commands not completed due to a brown-out condition may cause the memory location (volatile and non-volatile) to become corrupted.
The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and SPI operation are described in their own sections. The Device Commands commands are discussed in Section 7.0.
4.1
POR/BOR Operation
4.2
Memory Map
The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less then 1.8V. When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed.
The device memory is 16 locations that are 9-bits wide (16x9 bits). This memory space contains both volatile and non-volatile locations (see Table 4-1).
TABLE 4-1:
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
MEMORY MAP
Function Memory Type RAM RAM EEPROM EEPROM RAM RAM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM
4.1.1
POWER-ON RESET
When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage the following happens: * Volatile wiper register is loaded with value in the corresponding non-volatile wiper register * The TCON register is loaded it's default value * The device is capable of digital operation
Volatile Wiper 0 Volatile Wiper 1 Non-Volatile Wiper 0 Non-Volatile Wiper 1 Volatile TCON Register Status Register Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM Data EEPROM
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4.2.1 NON-VOLATILE MEMORY (EEPROM) 4.2.1.4 Special Features
This memory can be grouped into two uses of non-volatile memory. These are: * General Purpose Registers * Non-Volatile Wiper Registers The non-volatile wipers starts functioning below the devices VPOR/VBOR trip point. There are 3 non-volatile bits that are not directly mapped into the address space. These bits control the following functions: * EEPROM Write Protect * WiperLock Technology for Non-Volatile Wiper 0 * WiperLock Technology for Non-Volatile Wiper 1 The operation of WiperLock Technology is discussed in Section 5.3. The state of the WL0, WL1, and WP bits is reflected in the STATUS register (see Register 4-1).
4.2.1.1
General Purpose Registers
These locations allow the user to store up to 10 (9-bit) locations worth of information.
EEPROM Write Protect
All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write commands to the internal EEPROM are prevented. Write Protect (WP) can be enabled/disabled by two methods. These are: * External WP Hardware pin (MCP42X1 devices only) * Non-Volatile configuration bit High Voltage commands are required to enable and disable the nonvolatile WP bit. These commands are shown in Section 7.9 "Modify Write Protect or WiperLock Technology (High Voltage)". To write to EEPROM, both the external WP pin and the internal WP EEPROM bit must be disabled. Write Protect does not block commands to the volatile registers.
4.2.1.2
Non-Volatile Wiper Registers
These locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are up to two registers, one for each resistor network. The non-volatile wiper register enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value.
4.2.1.3
Factory Initialization of Non-Volatile Memory (EEPROM)
The Non-Volatile Wiper values will be initialized to mid-scale value. This is shown in Table 4-2. The General purpose EEPROM memory will be programmed to a default value of 0xFF. It is good practice in the manufacturing flow to configure the device to your desired settings.
4.2.2
VOLATILE MEMORY (RAM)
TABLE 4-2:
DEFAULT FACTORY SETTINGS SELECTION
Default POR Wiper Setting Wiper Code WiperLockTM Technology and Write Protect Setting
There are four Volatile Memory locations. These are: * Volatile Wiper 0 * Volatile Wiper 1 (Dual Resistor Network devices only) * Status Register * Terminal Control (TCON) Register The volatile memory starts functioning at the RAM retention voltage (VRAM).
Resistance Code
Typical RAB Value
8-bit 7-bit
-502 -103 -503 -104
5.0 k 10.0 k 50.0 k
Mid-scale Mid-scale Mid-scale
80h 80h 80h 80h
40h 40h 40h 40h
Disabled Disabled Disabled Disabled
100.0 k Mid-scale
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4.2.2.1 Status (STATUS) Register
This register contains 5 status bits. These bits show the state of the WiperLock bits, the Shutdown bit the Write Protect bit, and if an EEPROM write cycle is active. The STATUS register can be accessed via the READ commands. Register 4-1 describes each STATUS register bit. The STATUS register is placed at Address 05h.
REGISTER 4-1:
R-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 8-5 bit 4 R-1
STATUS REGISTER
R-1 D8:D5 R-1 R-0 EEWA R-x WL1 (1) R-x WL0
(1)
R-x SHDN
R-x WP (1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
D8:D5: Reserved. Forced to "1" EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = An EEPROM Write cycle is NOT currently occurring WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 "WiperLockTM Technology" for further information) WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are "Locked" (Write Protected) 0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified Note: The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1 bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value.
bit 3
bit 2
WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 "WiperLockTM Technology" for further information) The WiperLock Technology bits (WLx) prevents the Volatile and Non-Volatile Wiper 0 addresses and the TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are "Locked" (Write Protected) 0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified Note: The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0 bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value.
bit 1
SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.4 "Shutdown" for further information) This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects the Terminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in Hardware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register may be read. 1 = MCP4XXX is in the Hardware Shutdown state 0 = MCP4XXX is NOT in the Hardware Shutdown state Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is Not directly written, but reflects the system state (for this feature).
Note 1:
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REGISTER 4-1:
bit 0
STATUS REGISTER (CONTINUED)
WP: EEPROM Write Protect Status bit (Refer to Section "EEPROM Write Protect" for further information) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON register value (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. High Voltage commands are required to enable and disable the internal WP EEPROM bit. 1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is Not directly written, but reflects the system state (for this feature).
Note 1:
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4.2.2.2 Terminal Control (TCON) Register
This register contains 8 control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register 4-2 describes each bit of the TCON register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. The value that is written to this register will appear on the resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited. On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The HostController needs to detect the POR/BOR event and then update the Volatile TCON register value.
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REGISTER 4-2:
R-1 D8 bit 8 Legend: R = Readable bit -n = Value at POR bit 8 bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TCON BITS (1, 2)
R/W-1 R1A R/W-1 R1W R/W-1 R1B R/W-1 R0HW R/W-1 R0A R/W-1 R0W R/W-1 R0B bit 0
R/W-1 R1HW
D8: Reserved. Forced to "1" R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the "shutdown" configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 1 is forced to the hardware pin "shutdown" configuration R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the "shutdown" configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 0 is forced to the hardware pin "shutdown" configuration R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the state of the TCON bits. These bits do not affect the wiper register values.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
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5.0 RESISTOR NETWORK
5.1 Resistor Ladder Module
The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: * Resistor Ladder * Wiper * Shutdown (Terminal Connections) Devices have either one or two resistor networks, These are referred to as Pot 0 and Pot 1. The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 5-1). The end points of the resistor ladder are connected to analog switches which are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B). For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B). Equation 5-1 shows the calculation for the step resistance.
A
8-Bit N= 257 (1) (100h) 256 (FFh) 255 (FEh) 7-Bit N= 128 (80h) 127 (7Fh) 126 (7Eh)
RS
RW
RS
RW (1) RW
(1)
EQUATION 5-1:
R AB R S = ------------( 256 )
RS CALCULATION
8-bit Device
R RAB S
W
RW 1 (1) (01h) 0 (00h) 1 (01h) 0 (00h) R AB R S = ------------( 128 ) 7-bit Device
RS
RW
(1)
Analog Mux
B
Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
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5.2 Wiper 5.3 WiperLockTM Technology
Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full-scale connections, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. The MCP4XXX device's WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. There are two WiperLock Technology configuration bits (WL0 and WL1). These bits prevent the Non-Volatile and Volatile addresses and bits for the specified resistor network from being written. The WiperLock technology prevents commands from doing the following: the serial
* Changing a volatile wiper value * Writing to a non-volatile wiper memory location * Changing the volatile TCON register value For either Resistor Network 0 or Resistor Network 1 (Potx), the WLx bit controls the following: * Non-Volatile Wiper Register * Volatile Wiper Register * Volatile TCON register bits RxHW, RxA, RxW, and RxB High Voltage commands are required to enable and disable WiperLock. Please refer to the Modify Write Protect or WiperLock Technology (High Voltage) command for operation.
5.3.1 EQUATION 5-2: RWB CALCULATION
8-bit Device R AB N R WB = ------------- + R W ( 256 ) N = 0 to 256 (decimal) R AB N R WB = ------------- + R W ( 128 ) N = 0 to 128 (decimal) 7-bit Device
POR/BOR OPERATION WHEN WIPERLOCK TECHNOLOGY ENABLED
The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile Wiper register value with the Non-Volatile Wiper register value, refer to Section 4.1.
TABLE 5-1:
VOLATILE WIPER VALUE VS. WIPER POSITION MAP
Properties
Wiper Setting 7-bit Pot 8-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h Reserved (Full Scale (W = A)), Increment and Decrement commands ignored Full Scale (W = A), Increment commands ignored W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Decrement command ignored
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5.4 Shutdown
5.4.2
Shutdown is used to minimize the device's current consumption. The MCP4XXX has two methods to achieve this. These are: * Hardware Shutdown Pin (SHDN) * Terminal Control Register (TCON) The Hardware Shutdown pin is backwards compatible with the MCP42XXX devices.
TERMINAL CONTROL REGISTER (TCON)
The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. This register is shown in Register 4-2. The RxHW bits forces the selected resistor network into the same state as the SHDN pin. Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. Note: When the RxHW bit forces the resistor network into the hardware SHDN state, the state of the TCON register RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN state, the TCON register RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits.
5.4.1
HARDWARE SHUTDOWN PIN (SHDN)
The SHDN pin is available on the dual potentiometer devices. When the SHDN pin is forced active (VIL): * The P0A and P1A terminals are disconnected * The P0W and P1W terminals are simultaneously connect to the P0B and P1B terminals, respectively (see Figure 5-2) * The Serial Interface is NOT disabled, and all Serial Interface activity is executed * Any EEPROM write cycles are completed The Hardware Shutdown pin mode does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When the Shutdown mode is exited (SHDN pin is inactive (VIH)): * The device returns to the Wiper setting specified by the Volatile Wiper value * The TCON register bits return to controlling the terminal connection state A Resistor Network W
5.4.3
INTERACTION OF SHDN PIN AND TCON REGISTER
Figure 5-3 shows how the SHDN pin signal and the RxHW bit signal interact to control the hardware shutdown of each resistor network (independently). Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually "shutdown" while the hardware pin forces both resistor networks to be "shutdown" at the same time.
SHDN (from pin) RxHW (from TCON register) B
To Pot x Hardware Shutdown Control
FIGURE 5-2: Hardware Shutdown Resistor Network Configuration.
FIGURE 5-3: Interaction.
RxHW bit and SHDN pin
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NOTES:
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6.0 SERIAL INTERFACE (SPI)
The MCP4XXX devices support the SPI serial protocol. This SPI operates in the slave mode (does not generate the serial clock). The SPI interface uses up to four pins. These are: * * * * CS - Chip Select SCK - Serial Clock SDI - Serial Data In SDO - Serial Data Out Typical SPI Interfaces are shown in Figure 6-1. In the SPI interface, The Master's Output pin is connected to the Slave's Input pin and the Master's Input pin is connected to the Slave's Output pin. The MCP4XXX SPI's module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The SPI mode is determined by the state of the SCK pin (VIH or VIL) on the when the CS pin transitions from inactive (VIH) to active (VIL or VIHH). All SPI interface signals are high-voltage tolerant.
Typical SPI Interface Connections Host Controller MCP4XXX SDO SDI SCK I/O (1) Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI) Host Controller MCP41X1 SDO SDI SCK I/O
(1)
( Master Out - Slave In (MOSI) ) ( Master In - Slave Out (MISO) )
SDI SDO SCK CS
SDI/SDO R1(2)
SDI SDO
SCK CS
Alternate MCP41X1 SPI Interface Connections (Host Controller Firmware SPI) Host Controller MCP41X1 SDI/SDO SDI SDO I/O (SCK) I/O (1) SCK CS
I/O (SDO/SDI)
Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented. 2: R1 must be sized to ensure VIL and VIH of the devices are met.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
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6.1 SDI, SDO, SCK, and CS Operation
6.1.3
Note:
SDI/SDO
MCP41X1 Devices Only .
The operation of the four SPI interface pins are discussed in this section. These pins are: * * * * SDI (Serial Data In) SDO (Serial Data Out) SCK (Serial Clock) CS (Chip Select)
For device packages that do not have enough pins for both an SDI and SDO pin, the SDI and SDO functionality is multiplexed onto a single I/O pin called SDI/SDO. The SDO will only be driven for the command error bit (CMDERR) and during the data bits of a read command (after the memory address and command has been received).
The serial interface works on either 8-bit or 16-bit boundaries depending on the selected command. The Chip Select (CS) pin frames the SPI commands.
6.1.1
SERIAL DATA IN (SDI)
6.1.3.1
SDI/SDO Operation
The Serial Data In (SDI) signal is the data signal into the device. The value on this pin is latched on the rising edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out of the device. The value on this pin is driven on the falling edge of the SCK signal. Once the CS pin is forced to the active level (VIL or VIHH), the SDO pin will be driven. The state of the SDO pin is determined by the serial bit's position in the command, the command selected, and if there is a command error state (CMDERR).
Figure 6-2 shows a block diagram of the SDI/SDO pin. The SDI signal has an internal "smart" pull-up. The value of this pull-up determines the frequency that data can be read from the device. An external pull-up can be added to the SDI/SDO pin to improve the rise time and therefore improve the frequency that data can be read. Note: To support the High voltage requirement of the SDI function, the SDO function is an open-drain output.
Data written on the SDI/SDO pin can be at the maximum SPI frequency. Note: Care must be take to ensure that a Drive conflict does not exist between the Host Controllers SDO pin (or software SDI/SDO pin) and the MCP41x1 SDI/SDO pin (see Figure 6-1).
On the falling edge of the SCK pin during the C0 bit (see Figure 7-1), the SDI/SDO pin will start outputting the SDO value. The SDO signal overrides the control of the smart pull-up, such that whenever the SDI/SDO pin is outputting data, the smart pull-up is enabled. The SDI/SDO pin will change from an input (SDI) to an output (SDO) after the state machine has received the Address and Command bits of the Command Byte. If the command is a Read command, then the SDI/SDO pin will remain an output for the remainder of the command. For any other command, the SDI/SDO pin returns to an input.
"smart" pull-up SDI/SDO Open Drain Control Logic SDO SDI
FIGURE 6-2: Diagram.
Serial I/O Mux Block
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6.1.4 SERIAL CLOCK (SCK) (SPI FREQUENCY OF OPERATION) 6.1.5 THE CS SIGNAL
The SPI interface is specified to operate up to 10 MHz. The actual clock rate depends on the configuration of the system and the serial command used. Table 6-1 shows the SCK frequency for different configurations. The Chip Select (CS) signal is used to select the device and frame a command sequence. To start a command, or sequence of commands, the CS signal must transition from the inactive state (VIH) to an active state (VIL or VIHH). After the CS signal has gone active, the SDO pin is driven and the clock bit counter is reset. Note: There is a required delay after the CS pin goes active to the 1st edge of the SCK pin.
TABLE 6-1:
SCK FREQUENCY
Command Write, Increment, Decrement
Memory Type Access Read Non-Volatile Memory Volatile Memory
SDI, SDO 10 MHz 10 MHz (2, 3) (4) SDI/SDO 250 kHz 10 MHz (2, 3)
(1)
If an error condition occurs for an SPI command, then the Command byte's Command Error (CMDERR) bit (on the SDO pin) will be driven low (VIL). To exit the error condition, the user must take the CS pin to the VIH level. When the CS pin returns to the inactive state (VIH) the SPI module resets (including the address pointer). While the CS pin is in the inactive state (VIH), the serial interface is ignored. This allows the Host Controller to interface to other SPI devices using the same SDI, SDO, and SCK signals. The CS pin has an internal pull-up resistor. The resistor is disabled when the voltage on the CS pin is at the VIL level. This means that when the CS pin is not driven, the internal pull-up resistor will pull this signal to the VIH level. When the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption. The high voltage capability of the CS pin allows High Voltage commands. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled.
SDI, SDO 10 MHz SDI/SDO 250 kHz (4)
(1)
10 MHz 10 MHz
Note 1: MCP41X1 devices only 2: Non-Volatile memory does not support the Increment or Decrement command. 3: After a Write command, the internal write cycle must complete before the next SPI command is received. 4: This is the maximum clock frequency without an external pull-up resistor.
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6.2 The SPI Modes 6.3 SPI Waveforms
The SPI module supports two (of the four) standard SPI modes. These are Mode 0,0 and 1,1. The mode is determined by the state of the SDI pin on the rising edge of the 1st clock bit (of the 8-bit byte). Figure 6-3 through Figure 6-8 show the different SPI command waveforms. Figure 6-3 and Figure 6-4 are read and write commands. Figure 6-5 and Figure 6-6 are read commands when the SDI and SDO pins are multiplexed on the same pin (SDI/SDO). Figure 6-7 and Figure 6-8 are increment and decrement commands. The high voltage increment and decrement commands are used to enable and disable WiperLock Technology and Write Protect.
6.2.1
MODE 0,0
In Mode 0,0: SCK idle state = low (VIL), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
6.2.2
MODE 1,1
In Mode 1,1: SCK idle state = high (VIH), data is clocked in on the SDI pin on the rising edge of SCK and clocked out on the SDO pin on the falling edge of SCK.
VIHH VIL
VIH CS SCK
Write to SSPBUF CMDERR bit SDO SDI Input Sample bit15 bit14 bit13 bit12 bit11 AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 bit10 bit9 X bit9 bit8 D8 bit8 bit7 D7 bit7 bit6 D6 bit6 bit5 D5 bit5 bit4 D4 bit4 bit3 D3 bit3 bit2 bit1 bit0 D0 bit0
C1
C0
D2 D1 bit2 bit1
FIGURE 6-3:
VIHH VIL
16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
VIH CS
SCK Write to SSPBUF SDO SDI Input Sample bit15 bit14 bit13 bit12 bit11
CMDERR bit bit10 bit9 X bit9 bit8 D8 bit8 bit7 D7 bit7 bit6 D6 bit6 bit5 D5 bit5 bit4 D4 bit4 bit3 D3 bit3 bit2 bit1 bit0 D0 bit0
AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12
C1
C0
D2 D1 bit2 bit1
FIGURE 6-4:
16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
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VIH CS SCK VIHH VIL
Write to SSPBUF SDO SDI Input Sample AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 C1 1 C0 1
CMDERR bit D9 D8 D7 bit9 bit8 bit7 (1) (1) (1)
D6 bit6 (1)
D5 bit5 (1)
D4 bit4 (1)
D3 bit3 (1)
D2 bit2 (1)
D1 bit1 (1)
D0 bit0 (1)
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven
FIGURE 6-5: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 1,1).
VIH CS VIHH VIL
SCK Write to SSPBUF SDO SDI Input Sample AD3 AD2 AD1 AD0 bit15 bit14 bit13 bit12 C1 1 C0 1
CMDERR bit D8 D7 X bit9 bit8 bit7 (1) (1) (1)
D6 bit6 (1)
D5 bit5 (1)
D4 bit4 (1)
D3 bit3 (1)
D2 bit2 (1)
D1 bit1 (1)
D0 bit0 (1)
Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven
FIGURE 6-6: 16-Bit Read Command for Devices with SDI/SDO multiplexed SPI Waveform (Mode 0,0).
(c) 2008 Microchip Technology Inc.
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CS VIH VIHH VIL SCK
Write to SSPBUF CMDERR bit "1" = "Valid" Command/Address "0" = "Invalid" Command/Address SDO SDI bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AD3 bit7
AD2
AD1
AD0
C1
C0
X
X bit0
Input Sample
FIGURE 6-7: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 1,1).
VIHH VIL
VIH CS
SCK Write to SSPBUF
CMDERR bit "1" = "Valid" Command/Address "0" = "Invalid" Command/Address bit7 AD3 bit7 bit6 AD2 bit5 AD1 bit4 AD0 bit3 C1 bit2 C0 bit1 X bit0 X bit0
SDO SDI
Input Sample
FIGURE 6-8: 8-Bit Commands (Increment, Decrement, Modify Write Protect or WiperLock Technology) - SPI Waveform with PIC MCU (Mode 0,0).
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7.0 DEVICE COMMANDS
7.1 Command Byte
The MCP4XXX's SPI command format supports 16 memory address locations and four commands. Each command has two modes. These are: * Normal Serial Commands * High-Voltage Serial Commands Normal serial commands are those where the CS pin is driven to VIL. With High-Voltage Serial Commands, the CS pin is driven to VIHH. In each mode, there are four possible commands. These commands are shown in Table 7-1. The 8-bit commands (Increment Wiper and Decrement Wiper commands) contain a Command Byte, see Figure 7-1, while 16-bit commands (Read Data and Write Data commands) contain a Command Byte and a Data Byte. The Command Byte contains two data bits, see Figure 7-1. Table 7-2 shows the supported commands for each memory location and the corresponding values on the SDI and SDO pins. Table 7-3 shows an overview of all the SPI commands and their interaction with other device features. The Command Byte has three fields, the Address, the Command, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). This is for the Write command. The device memory is accessed when the master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte's AD3:AD0 bits. The action desired is contained in the Command Byte's C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock Technology and Software Write Protect. As the Command Byte is being loaded into the device (on the SDI pin), the device's SDO pin is driving. The SDO pin will output high bits for the first six bits of that command. On the 7th bit, the SDO pin will output the CMDERR bit state (see Section 7.3 "Error Condition"). The 8th bit state depends on the the command selected.
TABLE 7-1:
COMMAND BIT OVERVIEW
# of Bits 16-Bits 16-Bits 8-Bits 8-Bits Operates on Volatile/ Non-Volatile memory Both Both Volatile Only Volatile Only
C1:C0 Bit Command States
11 00 01 10
Read Data Write Data Increment (1) Decrement (1)
Note 1: High Voltage Increment and Decrement commands on select non-volatile memory locations enable/disable WiperLock Technology and the software Write Protect feature. 8-bit Command Command Byte AAAACCDD DDDD1098 3210 Memory Address Data Bits Command Bits 16-bit Command Command Byte Data Byte
AAAACCDDDDDDDDDD DDDD109876543210 3210 Memory Address Command Bits Data Bits
Command Bits CC 10 0 0 = Write Data 0 1 = INCR 1 0 = DECR 1 1 = Read Data
FIGURE 7-1:
General SPI Command Formats.
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TABLE 7-2:
Address Command Value 00h Function Volatile Wiper 0 Write Data Read Data Increment Wiper Decrement Wiper 01h Volatile Wiper 1 Write Data Read Data Increment Wiper Decrement Wiper 02h NV Wiper 0 Write Data Read Data HV Inc. (WL0 DIS) (3) HV Dec. (WL0 EN) (4) 03h NV Wiper 1 Write Data Read Data HV Inc. (WL1 DIS) (3) HV Dec. (WL1 EN) (4) 04h (5) Volatile TCON Register 05h (5) Status Register 06h (5) Data EEPROM 07h (5) Data EEPROM 08h (5) Data EEPROM 09h (5) Data EEPROM 0Ah (5) Data EEPROM 0Bh (5) Data EEPROM 0Ch (5) Data EEPROM 0Dh (5) Data EEPROM 0Eh (5) Data EEPROM 0Fh Data EEPROM Write Data Read Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data Write Data Read Data HV Inc. (WP DIS) (3) HV Dec. (WP EN) (4) Note 1: 2: 3: 4: 5:
MEMORY MAP AND THE SUPPORTED COMMANDS
Data (10-bits) (1) nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn nn nnnn nnnn -- -- SPI String (Binary) MOSI (SDI pin) 0000 00nn nnnn nnnn 0000 11nn nnnn nnnn 0000 0100 0000 1000 0001 00nn nnnn nnnn 0001 11nn nnnn nnnn 0001 0100 0001 1000 0010 00nn nnnn nnnn 0010 11nn nnnn nnnn 0010 0100 0010 1000 0011 00nn nnnn nnnn 0011 11nn nnnn nnnn 0011 0100 0011 1000 0100 00nn nnnn nnnn 0100 11nn nnnn nnnn 0101 11nn nnnn nnnn 0110 00nn nnnn nnnn 0110 11nn nnnn nnnn 0111 00nn nnnn nnnn 0111 11nn nnnn nnnn 1000 00nn nnnn nnnn 1000 11nn nnnn nnnn 1001 00nn nnnn nnnn 1001 11nn nnnn nnnn 1010 00nn nnnn nnnn 1010 11nn nnnn nnnn 1011 00nn nnnn nnnn 1011 11nn nnnn nnnn 1100 00nn nnnn nnnn 1100 11nn nnnn nnnn 1101 00nn nnnn nnnn 1101 11nn nnnn nnnn 1110 00nn nnnn nnnn 1110 11nn nnnn nnnn 1111 00nn nnnn nnnn 1111 11nn nnnn nnnn 1111 0100 1111 1000 MISO (SDO pin) (2) 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111 1111 111n nnnn nnnn 1111 1111 1111 1111
The Data Memory is only 9-bits wide, so the MSb is ignored by the device. All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combination is a command error state and the CMDERR bit will be clear. Disables WiperLock Technology for wiper 0 or wiper 1, or disables Write Protect. Enables WiperLock Technology for wiper 0 or wiper 1, or enables Write Protect. Reserved addresses: Increment or Decrement commands are invalid for these addresses.
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7.2 Data Byte
7.3.1 ABORTING A TRANSMISSION
Only the Read Command and the Write Command use the Data Byte, see Figure 7-1. These commands concatenate the 8-bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to Full Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused, and corresponds to the position on the SDO data of the CMDERR bit. All SPI transmissions must have the correct number of SCK pulses to be executed. The command is not executed until the complete number of clocks have been received. Some commands also require the CS pin to be forced inactive (VIH). If the CS pin is forced to the inactive state (VIH) the serial interface is reset. Partial commands are not executed. SPI is more susceptible to noise than other bus protocols. The most likely case is that this noise corrupts the value of the data being clocked into the MCP4XXX or the SCK pin is injected with extra clock pulses. This may cause data to be corrupted in the device, or a command error to occur, since the address and command bits were not a valid combination. The extra SCK pulse will also cause the SPI data (SDI) and clock (SCK) to be out of sync. Forcing the CS pin to the inactive state (VIH) resets the serial interface. The SPI interface will ignore activity on the SDI and SCK pins until the CS pin transition to the active state is detected (VIH to VIL or VIH to VIHH). Note 1: When data is not being received by the MCP4XXX, It is recommended that the CS pin be forced to the inactive level (VIL) 2: It is also recommended that long continuous command strings should be broken down into single commands or shorter continuous command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI commands.
7.3
Error Condition
The CMDERR bit indicates if the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination (see Table 4-1). The CMDERR bit is high if the combination is valid and low if the combination is invalid. The command error bit will also be low if a write to a Non-Volatile Address has been specified and another SPI command occurs before the CS pin is driven inactive (VIH). SPI commands that do not have a multiple of 8 clocks are ignored. Once an error condition has occurred, any following commands are ignored. All following SDO bits will be low until the CMDERR condition is cleared by forcing the CS pin to the inactive state (VIH).
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7.4 Continuous Commands
The device supports the ability to execute commands continuously. While the CS pin is in the active state (VIL or VIHH). Any sequence of valid commands may be received. The following example is a valid sequence of events: 1. 2. 3. 4. 5. 6. 7. 8. CS pin driven active (VIL or VIHH). Read Command. Increment Command (Wiper 0). Increment Command (Wiper 0). Decrement Command (Wiper 1). Write Command (Volatile memory). Write Command (Non-Volatile memory). CS pin driven inactive (VIH). Note 1: It is recommended that while the CS pin is active, only one type of command should be issued. When changing commands, it is recommended to take the CS pin inactive then force it back to the active state. 2: It is also recommended that long command strings should be broken down into shorter command strings. This reduces the probability of noise on the SCK pin corrupting the desired SPI command string.
TABLE 7-3:
COMMANDS
# of Bits 16-Bits 16-Bits 8-Bits 8-Bits 16-Bits 16-Bits 8-Bits 8-Bits 8-Bits Operates on High Writes Volatile/ Voltage Value in Non-Volatile (VIHH) on EEPROM CS pin? memory Yes (1) -- -- -- Yes -- -- -- --
(2)
Command Name
Impact on WiperLock or Write Protect unlocked (1) unlocked (1) unlocked
(1)
Works when Wiper is "locked"? No No No No No Yes No No Yes
Write Data Read Data Increment Wiper Decrement Wiper High Voltage Write Data High Voltage Read Data High Voltage Increment Wiper High Voltage Decrement Wiper Modify Write Protect or WiperLock Technology (High Voltage) Enable Modify Write Protect or WiperLock Technology (High Voltage) Disable
Both Both Volatile Only Volatile Only Both Both Volatile Only Volatile Only Non-Volatile Only (2) Non-Volatile Only (3)
-- -- -- -- Yes Yes Yes Yes Yes
unlocked (1) unchanged unchanged unchanged unchanged locked/ protected (2) unlocked/ unprotected (3)
8-Bits
-- (3)
Yes
Yes
Note 1: This command will only complete if wiper is "unlocked" (WiperLock Technology is Disabled). 2: If the command is executed using address 02h or 03h, then that corresponding wiper is locked or if with address 0Fh, then Write Protect is enabled. 3: If the command is executed using with address 02h or 03h, then that corresponding wiper is unlocked or if with address 0Fh, then Write Protect is disabled.
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7.5 Write Data Normal and High Voltage
7.5.2 SINGLE WRITE TO NON-VOLATILE MEMORY
The sequence to write to to a single non-volatile memory location is the same as a single write to volatile memory with the exception that after the CS pin is driven inactive (VIH), the EEPROM write cycle (tWC) is started. A write cycle will not start if the write command isn't exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations. After the CS pin is driven inactive (VIH), the serial interface may immediately be re-enabled by driving the CS pin to the active state (VILor VIHH). During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. Once a write command to a Non-Volatile memory location has been received, NO other SPI commands should be received before the CS pin transitions to the inactive state (VIH) or the current SPI command will have a Command Error (CMDERR) occur.
The Write command is a 16-bit command. The Write Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-2. A Write command to a Volatile memory location changes that location after a properly formatted Write Command (16-clock) have been received. A Write command to a Non-Volatile memory location will only start a write cycle after a properly formatted Write Command (16-clock) have been received and the CS pin transitions to the inactive state (VIH). Note: Writes to certain memory locations will be dependant on the state of the WiperLock Technology bits and the Write Protect bit.
7.5.1
SINGLE WRITE TO VOLATILE MEMORY
The write operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VIL). The 16-bit Write Command (Command Byte and Data Byte) is then clocked in on the SCK and SDI pins. Once all 16 bits have been received, the specified volatile address is updated. A write will not occur if the write command isn't exactly 16 clocks pulses. This protects against system issues from corrupting the Non-Volatile memory locations. Figure 6-3 and Figure 6-4 show possible waveforms for a single write. COMMAND BYTE A D 3 1 SDO 1 SDI A D 2 1 1 A D 1 1 1 A D 0 1 1 0 0 D 9 1 0 D 8 1 0 D 7 1 0 D 6 1 0 DATA BYTE D 5 1 0 D 4 1 0 D 3 1 0 D 2 1 0
D 1 1 0
D 0 1 Valid Address/Command combination 0 Invalid Address/Command combination (1)
1 1
1 1
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
Write Command - SDI and SDO States.
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7.5.3 CONTINUOUS WRITES TO VOLATILE MEMORY 7.5.4 CONTINUOUS WRITES TO NON-VOLATILE MEMORY
Continuous writes are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. COMMAND BYTE SDI SDO A D 3 1 A D 3 1 A D 3 1 A D 2 1 A D 2 1 A D 2 1 A D 1 1 A D 1 1 A D 1 1 A D 0 1 A D 0 1 A D 0 1 0 0 D 9 1* D 9 1* D 9 1* D 8 1 D 8 1 D 8 1 D 7 1 D 7 1 D 7 1 D 6 1 D 6 1 D 6 1 Continuous writes to non-volatile memory are not allowed, and attempts to do so will result in a command error (CMDERR) condition.
DATA BYTE D 5 1 D 5 1 D 5 1 D 4 1 D 4 1 D 4 1 D 3 1 D 3 1 D 3 1 D 2 1 D 2 1 D 2 1 D 1 1 D 1 1 D 1 1 D 0 1 D 0 1 D 0 1
1 0
1 0
1 0
1 0
1
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
Continuous Write Sequence (Volatile Memory only).
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7.6 Read Data Normal and High Voltage
7.6.1 SINGLE READ
The read operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 16-bit Read Command (Command Byte and Data Byte) is then clocked in on the SCK and SDI pins. The SDO pin starts driving data on the 7th bit (CMDERR bit) and the addressed data comes out on the 8th through 16th clocks. Figure 6-3 through Figure 6-6 show possible waveforms for a single read. Figure 6-5 and Figure 6-6 show the single read waveforms when the SDI and SDO signals are multiplexed on the same pin. For additional information on the multiplexing of these signals, refer to Section 6.1.3 "SDI/SDO".
The Read command is a 16-bit command. The Read Command can be issued to both the Volatile and Non-Volatile memory locations. The format of the command is shown in Figure 7-4. The first 6-bits of the Read command determine the address and the command. The 7th clock will output the CMDERR bit on the SDO pin. The remaining 9-clocks the device will transmit the 9 data bits (D8:D0) of the specified address (AD3:AD0). Figure 7-4 shows the SDI and SDO information for a Read command. During a write cycle (Write or High Voltage Write to a Non-Volatile memory location) the Read command can only read the Volatile memory locations. By reading the Status Register (04h), the Host Controller can determine when the write cycle has completed (via the state of the EEWA bit). COMMAND BYTE A D 3 1 1 A D 2 1 1 A D 1 1 1 A D 0 1 1 1 1 X X X X X DATA BYTE X X X
X
X
SDI SDO
1 1
1 1
1 0
D 8 0
D 7 0
D 6 0
D 5 0
D 4 0
D 3 0
D 2 0
D 1 0
D Valid Address/Command combination 0 0 Attempted Non-Volatile Memory Read during Non-Volatile Memory Write Cycle
READ DATA
FIGURE 7-4:
Read Command - SDI and SDO States.
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7.6.2 CONTINUOUS READS
Continuous reads allows the devices memory to be read quickly. Continuous reads are possible to all memory locations. If a non-volatile memory write cycle is occurring, then Read commands may only access the volatile memory locations. COMMAND BYTE A D 3 1 A D 2 1 A D 1 1 A D 0 1 1 1 X X X X X Figure 7-5 shows the sequence for three continuous reads. The reads do not need to be to the same memory address.
DATA BYTE X X X X X
SDI SDO
1
1
1* D 8 X X
D 7 X
D 6 X
D 5 X
D 4 X
D 3 X
D 2 X
D 1 X
D 0 X
A D 3 1
A D 2 1
A D 1 1
A D 0 1
1
1
1
1
1* D 8 X X
D 7 X
D 6 X
D 5 X
D 4 X
D 3 X
D 2 X
D 1 X
D 0 X
A D 3 1
A D 2 1
A D 1 1
A D 0 1
1
1
1
1
1* D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
Continuous Read Sequence.
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7.7 Increment Wiper Normal and High Voltage
7.7.1 SINGLE INCREMENT
The Increment Command is an 8-bit command. The Increment Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. An Increment Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. Increment commands provide a quick and easy method to modify the value of the volatile wiper location by +1 with minimal overhead. COMMAND BYTE (INCR COMMAND (n+1) ) SDI A D 3 1 SDO 1 A D 2 1 1 A D 1 1 1 A D 0 1 1 0 1 X X Typically, the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command. Figure 6-7 through Figure 6-8 show possible waveforms for a single increment. The increment operation requires that the CS pin be in the active state (VILor VIHH). Typically, the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). The 8-bit Increment Command (Command Byte) is then clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full Scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled. See Table 7-4 for additional information on the Increment Command versus the current volatile wiper value. The Increment operations only require the Increment command byte while the CS pin is active (VILor VIHH) for a single increment. After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs.
1 1
1 1
1* 0
1 Note 1, 2 0 Note 1, 3
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
TABLE 7-4:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
INCREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Reserved (Full-Scale (W = A)) Full-Scale (W = A) W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Increment Command Operates? No No
FIGURE 7-6: Increment Command SDI and SDO States.
Note: Table 7-2 shows the valid addresses for the Increment Wiper command. Other addresses are invalid.
Yes
Yes
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7.7.2 CONTINUOUS INCREMENTS
Continuous Increments are possible only when writing to the volatile memory registers (address 00h, and 01h). Figure 7-7 shows a Continuous Increment sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing an continuous Increment commands, the selected wiper will be altered from n to n+1 for each Increment command received. The wiper value will increment up to 100h on 8-bit devices and 80h on 7-bit devices. After the wiper value has reached Full-Scale (8-bit =100h, 7-bit =80h), the wiper value will not be incremented further. If the Wiper register has a value between 101h and 1FFh, the Increment command is disabled. COMMAND BYTE (INCR COMMAND (n+1) ) SDI A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 0 1 X X A D 3 1 0 1 1 Increment commands can be sent repeatedly without raising CS until a desired condition is met. The value in the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command. When executing a continuous command string, The Increment command can be followed by any other valid command. The wiper terminal will move after the command has been received (8th clock). After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. COMMAND BYTE (INCR COMMAND (n+3) ) X A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 0 1 X X
COMMAND BYTE (INCR COMMAND (n+2) ) A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 0 1 X
1 1 1 1
1 1 1 1
1* 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1* 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1* 0 0 0
1 0 0 0
Note 1, 2 Note 3, 4 Note 3, 4 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
Continuous Increment Command - SDI and SDO States.
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7.8 Decrement Wiper Normal and High Voltage
7.8.1 SINGLE DECREMENT
The Decrement Command is an 8-bit command. The Decrement Command can only be issued to volatile memory locations. The format of the command is shown in Figure 7-6. An Decrement Command to the volatile memory location changes that location after a properly formatted command (8-clocks) have been received. Decrement commands provide a quick and easy method to modify the value of the volatile wiper location by -1 with minimal overhead. COMMAND BYTE (DECR COMMAND (n+1)) SDI A D 3 1 SDO 1 A D 2 1 1 A D 1 1 1 A D 0 1 1 1 0 X X Typically the CS pin starts at the inactive state (VIH), but may be already be in the active state due to the completion of another command. Figure 6-7 through Figure 6-8 show possible waveforms for a single Decrement. The decrement operation requires that the CS pin be in the active state (VILor VIHH). Typically the CS pin will be in the inactive state (VIH) and is driven to the active state (VILor VIHH). Then the 8-bit Decrement Command (Command Byte) is clocked in on the SDI pin by the SCK pins. The SDO pin drives the CMDERR bit on the 7th clock. The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value. The Decrement commands only require the Decrement command byte, while the CS pin is active (VILor VIHH) for a single decrement. After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that unexpected transitions on the SCK pin do not cause the wiper setting to change. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs.
1 1
1 1
1* 0
1 Note 1, 2 0 Note 1, 3
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination all following SDO bits will be low until the CMDERR condition is cleared. (the CS pin is forced to the inactive state). 4: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be driven low until the CS pin is driven inactive (VIH).
TABLE 7-5:
Current Wiper Setting 7-bit Pot 3FFh 081h 080h 07Fh 041h 040h 03Fh 001h 000h 8-bit Pot 3FFh 101h 100h 0FFh 081 080h 07Fh 001 000h
DECREMENT OPERATION VS. VOLATILE WIPER VALUE
Wiper (W) Properties Reserved (Full-Scale (W = A)) Full-Scale (W = A) W=N W = N (Mid-Scale) W=N Zero Scale (W = B) Decrement Command Operates? No Yes
FIGURE 7-8: Decrement Command SDI and SDO States.
Note: Table 7-2 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid.
Yes
No
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7.8.2 CONTINUOUS DECREMENTS
Continuous Decrements are possible only when writing to the volatile memory registers (address 00h, 01h, and 04h). Figure 7-9 shows a continuous Decrement sequence for three continuous writes. The writes do not need to be to the same volatile memory address. When executing an continuous Decrement commands, the selected wiper will be altered from n to n-1 for each Decrement command received. The wiper value will decrement from the wipers Full Scale value (100h on 8-bit devices and 80h on 7-bit devices). Above the wipers Full-Scale value (8-bit =101h to 1FFh, 7-bit = 81h to FFh), the decrement command is disabled. If the Wiper register has a Zero Scale value (000h), then the wiper value will not decrement. See Table 7-4 for additional information on the Decrement Command vs. the current volatile wiper value. COMMAND BYTE (DECR COMMAND (n-1) ) SDI A D 3 1 1 SDO 1 1 A D 2 1 1 1 1 A D 1 1 1 1 1 A D 0 1 1 1 1 1 0 X X A D 3 1 0 1 1 Decrement commands can be sent repeatedly without raising CS until a desired condition is met. The value in the Volatile Wiper register can be read using a Read Command and written to the corresponding Non-Volatile Wiper EEPROM using a Write Command. When executing a continuous command string, The Decrement command can be followed by any other valid command. The wiper terminal will move after the command has been received (8th clock). After the wiper is decremented to the desired position, the CS pin should be forced to VIH to ensure that "unexpected" transitions (on the SCK pin do not cause the wiper setting to change). Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired decrement occurs.
COMMAND BYTE (DECR COMMAND (n-1) ) A D 2 1 0 1 1 A D 1 1 0 1 1 A D 0 1 0 1 1 1 0 X X
COMMAND BYTE (DECR COMMAND (n-1) ) A D 3 1 0 0 1 A D 2 1 0 0 1 A D 1 1 0 0 1 A D 0 1 0 0 1 1 0 X X
1 1 1 1
1 1 1 1
1* 0 1 1
1 0 1 1
1 0 1 1
1 0 1 1
1* 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1
1* 0 0 0
1 0 0 0
Note 1, 2 Note 3, 4 Note 3, 4 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h. 2: Valid Address/Command combination. 3: Invalid Address/Command combination. 4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
Continuous Decrement Command - SDI and SDO States.
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7.9 Modify Write Protect or WiperLock Technology (High Voltage) Enable and Disable
7.9.1 SINGLE ENABLE WRITE PROTECT OR WIPERLOCK TECHNOLOGY (HIGH VOLTAGE)
This command is a special case of the High Voltage Decrement Wiper and High Voltage Increment Wiper commands to the non-volatile memory locations 02h, 03h, and 0Fh. This command is used to enable or disable either the software Write Protect, wiper 0 WiperLock Technology, or wiper 1 WiperLock Technology. Table 7-6 shows the memory addresses, the High Voltage command and the result of those commands on the non-volatile WP, WL0, 0r WL1 bits. The format of the command is shown in Figure 7-8 (Enable) or Figure 7-6 (Disable).
Figure 6-7 through Figure 6-8 show possible waveforms for a single Modify Write Protect or WiperLock Technology command. A Modify Write Protect or WiperLock Technology Command will only start an EEPROM write cycle (twc) after a properly formatted Command (8-clocks) has been received and the CS pin transitions to the inactive state (VIH). After the CS pin is driven inactive (VIH), the serial interface may immediately be re-enabled by driving the CS pin to the active state (VILor VIHH). During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle.
TABLE 7-6:
Memory Address
ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY
Command's and Result High Voltage Decrement Wiper High Voltage Increment Wiper
00h Wiper 0 register is decremented Wiper 0 register is incremented 01h Wiper 1 register is decremented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled 04h (1) TCON register not changed, CMDERR bit is set TCON register not changed, CMDERR bit is set 05h - 0Eh (1) Reserved Reserved 0Fh WP is enabled WP is disabled Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.
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NOTES:
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8.0 APPLICATIONS EXAMPLES
5V Voltage Regulator PIC MCU SDI CS SCK WP SHDN SDO 3V Non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP414X/416X/424X/426X devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V).
MCP4XXX SDI CS SCK WP SHDN SDO
8.1
Split Rail Applications
All inputs that would be used to interface to a Host Controller support High Voltage on their input pin. This allows the MCP4XXX device to be used in split power rail applications. An example of this is a battery application where the PIC(R) MCU is directly powered by the battery supply (4.8V) and the MCP4XXX device is powered by the 3.3V regulated voltage. For SPI applications, these inputs are: * * * * * CS SCK SDI (or SDI/SDO) WP SHDN
FIGURE 8-1: System 1.
Voltage Regulator 3V PIC MCU SDI CS SCK WP SHDN SDO
Example Split Rail
5V
MCP4XXX SDI CS SCK WP SHDN SDO
Figure 8-1 through Figure 8-2 show three example split rail systems. In this system, the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (VOH). In Example #1 (Figure 8-1), the MCP4XXX interface input signals need to be able to support the PIC MCU output high voltage (VOH). If the split rail voltage delta becomes too large, then the customer may be required to do some level shifting due to MCP4XXX VOH levels related to Host Controller VIH levels. In Example #2 (Figure 8-2), the MCP4XXX interface input signals need to be able to support the lower voltage of the PIC MCU output high voltage level (VOH). Table 8-1 shows an example PIC microcontroller I/O voltage specifications and the MCP4XXX specifications. So this PIC MCU operating at 3.3V will drive a VOH at 2.64V, and for the MCP4XXX operating at 5.5V, the VIH is 2.47V. Therefore, the interface signals meet specifications.
FIGURE 8-2: System 2. TABLE 8-1:
PIC VDD 5.5 5.0 4.5 3.3 3.0 2.7 Note
(1)
Example Split Rail
VOH - VIH COMPARISONS
MCP4XXX (2) Comment VOH VDD VIH VOH
VIH
4.4 4.4 2.7 1.215 -- (3) 4.0 4.0 3.0 1.35 -- (3) 3.6 3.6 3.3 1.485 -- (3) 2.64 2.64 4.5 2.025 -- (3) 2.4 2.4 5.0 2.25 -- (3) 2.16 2.16 5.5 2.475 -- (3) 1: VOH minimum = 0.8 * VDD; VOL maximum = 0.6V VIH minimum = 0.8 * VDD; VIL maximum = 0.2 * VDD; 2: VOH minimum (SDA only) =; VOL maximum = 0.2 * VDD VIH minimum = 0.45 * VDD; VIL maximum = 0.2 * VDD 3: The only MCP4XXX output pin is SDO, which is Open-Drain (or Open-Drain with Internal Pull-up) with High Voltage Support
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8.2 Techniques to force the CS pin to VIHH
PIC10F206 GP0 MCP4XXX GP2 C1 CS C2 R1
The circuit in Figure 8-3 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC(R) microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the CS pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately VDD.
PIC MCU IO1
TC1240A C+ VIN CSHDN VOUT R1 C2
FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage.
C1
8.3
Using Shutdown Modes
MCP402X CS
IO2
FIGURE 8-3: Using the TC1240A to generate the VIHH voltage.
The circuit in Figure 8-4 shows the method used on the MCP402X Non-volatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the CS pin to change the stored value of the wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User's Guide (DS51546) contains a complete schematic. GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the CS pin (VIL or VIH). For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V).
Figure 8-5 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to VDD and VSS.
Common A
Input A
W
To base of Transistor (or Amplifier)
B Input
Common B Balance Bias
FIGURE 8-5: Example Application Circuit using Terminal Disconnects.
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8.4 Design Considerations
8.4.2 LAYOUT CONSIDERATIONS
In the design of a system with the MCP4XXX devices, the following considerations should be taken into account: * Power Supply Considerations * Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4XXX's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended.
8.4.1
POWER SUPPLY CONSIDERATIONS
The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-6 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 F VDD 0.1 F PIC(R) Microcontroller
8.4.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-8, Figure 2-19, Figure 2-29, and Figure 2-39. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins supports two features. These are: * In-Circuit Accommodation of split rail applications and power supply sync issues * User configuration of the Non-Volatile EEPROM, Write Protect, and WiperLock feature Note: In many applications, the High Voltage will only be present at the manufacturing stage so as to "lock" the Non-Volatile wiper value (after calibration) and the contents of the EEPROM. This ensures that the since High Voltage is not present under normal operating conditions, that these values can not be modified.
A W
MCP414X/416X/ 424X/426X
U/D
B
CS
VSS
VSS
FIGURE 8-6: Connections.
Typical Microcontroller
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NOTES:
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9.0
9.1
DEVELOPMENT SUPPORT
Development Tools
9.2
Technical Documentation
Several development tools are available to assist in your design and evaluation of the MCP4XXX devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com.
Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents.
TABLE 9-1:
Board Name
DEVELOPMENT TOOLS
Part # Supported Devices MCP42XX MCP42XXX, MCP42XX, MCP4021, and MCP4011 Any 8-pin device in DIP, SOIC, MSOP, or TSSOP package Any 14-pin device in DIP, SOIC, or MSOP package
MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS Board MCP4XXX Digital Potentiometer Daughter Board (1) 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board 14-pin SOIC/MSOP/DIP Evaluation Board MCP4XXXDM-DB SOIC8EV SOIC14EV
Note 1: Requires the use of a PICDEM Demo board (see User's Guide for details)
TABLE 9-2:
Application Note Number AN1080 AN737 AN692 AN691 AN219 -- --
TECHNICAL DOCUMENTATION
Title Understanding Digital Potentiometers Resistor Variations Using Digital Potentiometers to Design Low Pass Adjustable Filters Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect Optimizing the Digital Potentiometer in Precision Circuits Comparing Digital Potentiometers to Mechanical Potentiometers Digital Potentiometer Design Guide Signal Chain Design Guide Literature # DS01080 DS00737 DS00692 DS00691 DS00219 DS22017 DS21825
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10.0
10.1
PACKAGING INFORMATION
Package Marking Information
Example: Part Number Code DAAJ DAAK DAAM DAAL DAAT DAAU DAAW DAAV Part Number MCP4142-502E/MF MCP4142-103E/MF MCP4142-104E/MF MCP4142-503E/MF MCP4162-502E/MF MCP4162-103E/MF MCP4162-104E/MF MCP4162-503E/MF Code DABC DABD DABF DABE DABG DABH DABK DABJ MCP4141-502E/MF MCP4141-103E/MF MCP4141-104E/MF MCP4141-503E/MF MCP4161-502E/MF MCP4161-103E/MF MCP4161-104E/MF MCP4161-503E/MF
8-Lead DFN (3x3)
XXXX XYWW NNN
DAAJ E816 256
8-Lead MSOP
Part Number MCP4141-502E/MS MCP4141-103E/MS MCP4141-104E/MS MCP4141-503E/MS MCP4161-502E/MS MCP4161-103E/MS MCP4161-104E/MS MCP4161-503E/MS
Code 414152 414113 414114 414153 416152 416113 416114 416153
Part Number MCP4142-502E/MS MCP4142-103E/MS MCP4142-104E/MS MCP4142-503E/MS MCP4162-502E/MS MCP4162-103E/MS MCP4162-104E/MS MCP4162-503E/MS
Code 414252 414213 414214 414253 416252 416213 416214 416253
Example
XXXXXX YWWNNN
414152 816256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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8-Lead PDIP Example
XXXXXXXX XXXXXNNN YYWW
8-Lead SOIC
4141-502 E/P e3 256 0816
Example
XXXXXXXX XXXXYYWW NNN
4141502E SN^^^0816 e3 256
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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MCP414X/416X/424X/426X
Package Marking Information (Continued)
10-Lead DFN (3x3) Example: Part Number MCP4242-502E/MF MCP4242-103E/MF MCP4242-104E/MF MCP4242-503E/MF 10-Lead MSOP Code BAEM BAEP BAER BAEQ Part Number MCP4262-502E/MF MCP4262-103E/MF MCP4262-104E/MF MCP4262-503E/MF Code BAEW BAEX BAEZ BAEY Example Part Number MCP4242-502E/MS MCP4242-103E/MS MCP4242-104E/MS MCP4242-503E/MS 14-Lead PDIP Code 424252 424213 424214 424253 Part Number MCP4262-502E/MS MCP4262-103E/MS MCP4262-104E/MS MCP4262-503E/MS Example Code 426252 426213 426214 426253
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APPENDIX A: REVISION HISTORY APPENDIX B:
Revision B (December 2008)
The following is the list of modifications: 1. 2. Updated IPU specifications to specify test conditions and new limit. Updated DFN and QFN package in "Package Types (top view)", to include Exposed Thermal Pad samples (EP). Added new descriptions in Section 3.0 "Pin Descriptions". Added new Development Tool support item. Updated Package Outline section.
MIGRATING FROM THE MCP41XXX AND MCP42XXX DEVICES
This is intended to give an overview of some of the differences to be aware of when migrating from the MCP41XXX and MCP42XXX devices.
B.1
MCP41XXX to MCP41XX Differences
3. 4. 5.
Here are some of the differences to be aware of: SI pin is now SDI/SDO pin, and the contents of the device memory can be read 2. Need to address the Terminal Connect Feature (TCON register) of MCP41XX 3. MCP41XX supports software Shutdown mode 4. New 5 k version 5. MCP41XX have 7-bit resolution options 6. MCP41XX are Non-Volatile 7. Alternate pinout versions (for Rheostat configuration) 8. Verify device's electrical specifications 9. Interface signals are now high voltage tolerant 10. Interface signals now have internal pull-up resistors 1.
Revision A (August 2007)
* Original Release of this Document.
B.2
MCP42XXX to MCP42XX Differences
Here are some of the differences to be aware of: 1. Hardware Reset (RS) pin replace by Hardware Write Protect (WP) pin 2. Daisy chaining of devices is no longer supported 3. SDO pin allows contents of device memory to be read 4. Need to address the Terminal Connect Feature (TCON register) of MCP42XX 5. MCP42XX supports software Shutdown mode 6. New 5 k version 7. MCP42XX have 7-bit resolution options 8. MCP42XX are Non-Volatile 9. Alternate package/pinout versions (for Rheostat configuration) 10. Verify device's electrical specifications 11. Interface signals are now high voltage tolerant 12. Interface signals now have internal pull-up resistors
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -XXX Resistance Version X Temperature Range /XX Package
Examples:
a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) a) b) c) d) e) f) g) h) XX MCP4141-502E/XX: MCP4141T-502E/XX: MCP4141-103E/XX: MCP4141T-103E/XX: MCP4141-503E/XX: MCP4141T-503E/XX: MCP4141-104E/XX: MCP4141T-104E/XX: MCP4142-502E/XX: MCP4142T-502E/XX: MCP4142-103E/XX: MCP4142T-103E/XX: MCP4142-503E/XX: MCP4142T-503E/XX: MCP4142-104E/XX: MCP4142T-104E/XX: MCP4161-502E/XX: MCP4161T-502E/XX: MCP4161-103E/XX: MCP4161T-103E/XX: MCP4161-503E/XX: MCP4161T-503E/XX: MCP4161-104E/XX: MCP4161T-104E/XX: MCP4162-502E/XX: MCP4162T-502E/XX: MCP4162-103E/XX: MCP4162T-103E/XX: MCP4162-503E/XX: MCP4162T-503E/XX: MCP4162-104E/XX: MCP4162T-104E/XX: MCP4241-502E/XX: MCP4241T-502E/XX: MCP4241-103E/XX: MCP4241T-103E/XX: MCP4241-503E/XX: MCP4241T-503E/XX: MCP4241-104E/XX: MCP4241T-104E/XX: MCP4242-502E/XX: MCP4242T-502E/XX: MCP4242-103E/XX: MCP4242T-103E/XX: MCP4242-503E/XX: MCP4242T-503E/XX: MCP4242-104E/XX: MCP4242T-104E/XX: MCP4261-502E/XX: MCP4261T-502E/XX: MCP4261-103E/XX: MCP4261T-103E/XX: MCP4261-503E/XX: MCP4261T-503E/XX: MCP4261-104E/XX: MCP4261T-104E/XX: MCP4262-502E/XX: MCP4262T-502E/XX: MCP4262-103E/XX: MCP4262T-103E/XX: MCP4262-503E/XX: MCP4262T-503E/XX: MCP4262-104E/XX: MCP4262T-104E/XX: = = = = = = = = 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device 5 k, 8LD Device T/R, 5 k, 8LD Device 10 k, 8-LD Device T/R, 10 k, 8LD Device 50 k, 8LD Device T/R, 50 k, 8LD Device 100 k, 8LD Device T/R, 100 k, 8LD Device
Device
MCP4141: MCP4141T: MCP4142: MCP4142T: MCP4161: MCP4161T: MCP4162: MCP4162T: MCP4241: MCP4241T: MCP4242: MCP4242T: MCP4261: MCP4261T: MCP4262: MCP4262T:
Single Non-Volatile 7-bit Potentiometer Single Non-Volatile 7-bit Potentiometer (Tape and Reel) Single Non-Volatile 7-bit Rheostat Single Non-Volatile 7-bit Rheostat (Tape and Reel) Single Non-Volatile 8-bit Potentiometer Single Non-Volatile 8-bit Potentiometer (Tape and Reel) Single Non-Volatile 8-bit Rheostat Single Non-Volatile 8-bit Rheostat (Tape and Reel) Dual Non-Volatile 7-bit Potentiometer Dual Non-Volatile 7-bit Potentiometer (Tape and Reel) Dual Non-Volatile 7-bit Rheostat Dual Non-Volatile 7-bit Rheostat (Tape and Reel) Dual Non-Volatile 8-bit Potentiometer Dual Non-Volatile 8-bit Potentiometer (Tape and Reel) Dual Non-Volatile 8-bit Rheostat Dual Non-Volatile 8-bit Rheostat (Tape and Reel)
Resistance Version:
502 103 503 104 I E MF ML MS P SN SL ST UN = = = = = = = =
= = = =
5 k 10 k 50 k 100 k
Temperature Range
= -40C to +85C (Industrial) = -40C to +125C (Extended) Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead Plastic Quad Flat No-lead (4x4 QFN), 16-lead Plastic Micro Small Outline (MSOP), 8-lead Plastic Dual In-line (PDIP) (300 mil), 8/14-lead Plastic Small Outline (SOIC), (150 mil), 8-lead Plastic Small Outline (SOIC), (150 mil), 14-lead Plastic Thin Shrink Small Outline (TSSOP), 14-lead Plastic Micro Small Outline (MSOP), 10-lead
Package
MF for 8/10-lead 3x3 DFN ML for 16-lead QFN MS for 8-lead MSOP P for 8/14-lead PDIP SN for 8-lead SOIC SL for 14-lead SOIC ST for 14-lead TSSOP UN for 10-lead MSOP
(c) 2008 Microchip Technology Inc.
DS22059B-page 85
MCP414X/416X/424X/426X
NOTES:
DS22059B-page 86
(c) 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2008 Microchip Technology Inc.
DS22059B-page 87
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
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EUROPE
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01/02/08
DS22059B-page 88
(c) 2008 Microchip Technology Inc.

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